IP-PCI/MT64【PDF 8/360 页】IP PCI 64BIT MASTER/TARGET

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Contents

Features ................................................................................................................................................... 4–2

PCI Testbench Files ............................................................................................................................... 4–2

Testbench Specifications ....................................................................................................................... 4–6

Master Transactor (mstr_tranx) ...................................................................................................... 4–7

PROCEDURES and TASKS Sections ........................................................................................ 4–7

INITIALIZATION Section ......................................................................................................... 4–8

USER COMMANDS Section ..................................................................................................... 4–8

Target Transactor (trgt_tranx) ................................................................................................. 4–12

FILE IO section .......................................................................................................................... 4–13

PROCEDURES and TASKS sections ...................................................................................... 4–13

Bus Monitor (monitor) ................................................................................................................... 4–14

Clock Generator (clk_gen) ............................................................................................................ 4–14

Arbiter (arbiter) .............................................................................................................................. 4–15

Pull Up (pull_up) ........................................................................................................................... 4–15

Local Reference Design ....................................................................................................................... 4–15

Local Target ..................................................................................................................................... 4–17

DMA Engine ................................................................................................................................... 4–17

Local Master .................................................................................................................................... 4–19

lm_lastn Generator ......................................................................................................................... 4–19

Prefetch ............................................................................................................................................ 4–19

LPM RAM ........................................................................................................................................ 4–19

Simulation Flow ................................................................................................................................... 4–20

Section II. PCI Compiler With SOPC Builder Flow

Chapter 5. Getting Started

Design Flow ............................................................................................................................................ 5–1

PCI Compiler with SOPC Builder Flow Design Walkthrough ....................................................... 5–2

Create a New Quartus II Project .................................................................................................... 5–3

Set Up the PCI-Avalon Bridge ........................................................................................................ 5–5

Add the Remaining Components to the SOPC Builder System ................................................ 5–7

Complete the Connections in SOPC Builder ................................................................................ 5–8

Generate the SOPC Builder System ............................................................................................... 5–9

Files Generated by SOPC Builder ................................................................................................ 5–10

Simulate the Design ............................................................................................................................. 5–11

Compile the Design ............................................................................................................................. 5–13

Program a Device ................................................................................................................................ 5–14

Upgrading Systems from a Previous Version ................................................................................. 5–15

Chapter 6. Parameter Settings

System Options-1 ...................................................................................................................................

PCI Device Mode ........................................................................................................................

PCI Target Performance .............................................................................................................

PCI Master Performance ............................................................................................................

Value of Multiple Pending Reads .......................................................................................................

6–1

6–1

6–3

6–5

6–6

viii

PCI Compiler

User Guide Version 11.1

Altera Corporation

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